307013-003 Datasheet, PDF (276/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.30
ILCL—Internal Link Capabilities List Register
Offset Address: 01A0–01A3h
Default Value: 00010006h
Attribute:
Size:
RO
32-bit
7.1.31
Bit
31:20
19:16
15:0
Description
Next Capability Offset (NEXT) — RO. Indicates this is the last item in the list.
Capability Version (CV) — RO. This field indicates the version of the capability
structure.
Capability ID (CID) — RO. This field indicates this is capability for DMI.
LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h
Default Value: 00012441h
Attribute:
Size:
RO/ R/WO
32-bit
Bit
Description
31:18 Reserved
17:15
Desktop ^{L1 Exit Latency (EL1) — L1 not supported on DMI.}
Only
17:15
Mobile/
Ultra
Mobile
Only
L1 Exit Latency (EL1) — RO. This field is set to 010b to indicate an exit latency of
2 us to 4 us.
14:12
L0s Exit Latency (EL0) — R/WO. This field indicates that exit latency is 128 ns to less
than 256 ns.
11:10
Active State Link PM Support (ASPM) — R/WO. This field indicates that L0s is
Desktop _{supported on DMI.}
Only
11:10
Mobile/
Ultra
Mobile
Only
Active State Link PM Support (ASPM) — R/WO. This field indicates the level of active
state power management on DMI.
00 = Neither L0s nor L1s are supported
01 = L0s Entry supported on DMI
10 = L1 Entry supported on DMI
11 = Both L0s and L1 supported on DMI
9:4 Maximum Link Width (MLW) — Indicates the maximum link width is 4 ports.
3:0 Maximum Link Speed (MLS) — Indicates the link speed is 2.5 Gb/s.
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Intel ^® ICH7 Family Datasheet