307013-003 Datasheet, PDF (449/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.13 SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 34h
00000000h
No
Core
Attribute:
Size:
Usage:
RO, R/WC
32-bit
ACPI or Legacy
Note:
If the corresponding _EN bit is set when the _STS bit is set, the ICH7 will cause an
SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs
of other registers that have enable bits). The ICH7 uses the same GPE0_EN register (I/
O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose
input events. ACPI OS assumes that it owns the entire GPE0_EN register per ACPI spec.
Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS,
and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns
off the enabled bit for any GPIx input signals that are not indicated as SCI general-
purpose events at boot, and exit from sleeping states. BIOS should define a dummy
control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
Bit
Description
31:27
26
(Desktop
and Mobile
Only)
26
(Ultra
Mobile
Only)
25
(Desktop
Only)
25
(Mobile
Only)
24:22
21
20
(Desktop
and Mobile
Only)
20
(Ultra
Mobile
Only)
19
Reserved
SPI_STS — RO. This bit will be set if the SPI logic is generating an SMI#. This bit
is read only because the sticky status and enable bits associated with this function
are located in the SPI registers.
Reserved
Intel^® ICH7DH Only:
EL_SMI_STS — RO. This bit will be set if the Intel Quick Resume Technology logic
is generating an SMI#. Writing a 1 to this bit clears this bit to ‘0’.
ICH7 and ICH7R Only:
Reserved.
Reserved
Reserved
MONITOR_STS — RO. This bit will be set if the Trap/SMI logic has caused the
SMI. This will occur when the processor or a bus master accesses an assigned
register (or a sequence of accesses). See Section 7.1.36 through Section 7.1.39
for details on the specific cause of the SMI.
PCI_EXP_SMI_STS — RO. PCI Express* SMI event occurred. This could be due
to a PCI Express PME event or Hot-Plug event.
Reserved
Reserved
Intel ^® ICH7 Family Datasheet
449