307013-003 Datasheet, PDF (306/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.1.4
Note:
PCISTS—PCI Status Register
(LAN Controller—B1:D8:F0)
Offset Address: 06h–07h
Default Value: 0290h
Attribute:
Size:
RO, R/WC
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE) — R/WC.
0 = Parity error Not detected.
1 = The Intel^® ICH7’s integrated LAN controller has detected a parity error on the PCI
bus (will be set even if Parity Error Response is disabled in the PCI Command
register).
Signaled System Error (SSE) — R/WC.
0 = Integrated LAN controller has not asserted SERR#
1 = The ICH7’s integrated LAN controller has asserted SERR#. SERR# can be routed to
cause NMI, SMI#, or interrupt.
Master Abort Status (RMA) — R/WC.
0 = Master Abort not generated
1 = The ICH7’s integrated LAN controller (as a PCI master) has generated a master
abort.
Received Target Abort (RTA) — R/WC.
0 = Target abort not received.
1 = The ICH7’s integrated LAN controller (as a PCI master) has received a target abort.
Signaled Target Abort (STA) — RO. Hardwired to 0. The device will not signal Target
Abort.
DEVSEL# Timing Status (DEV_STS) — RO.
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
0 = Parity error not detected (conditions below are not met).
1 = All of the following three conditions have been met:
1.
The LAN controller is acting as bus master
2.
The LAN controller has asserted PERR# (for reads) or detected PERR# asserted
(for writes)
3.
The Parity Error Response bit in the LAN controller’s PCI Command Register is
set.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast
back-to-back transactions.
User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66
MHz PCI.
Capabilities List (CAP_LIST) — RO.
0 = The EEPROM indicates that the integrated LAN controller does not support PCI
Power Management.
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power
Management.
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is
independent from the state of the Interrupt Enable bit in the command register.
Reserved
306
Intel ^® ICH7 Family Datasheet