307013-003 Datasheet, PDF (457/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.9.2
TCO_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCOBASE +02h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
10.9.3
Bit
Description
TCO Data In Value — R/W. This data register field is used for passing commands from
7:0 the OS to the SMI handler. Writes to this register will cause an SMI and set the
SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).
TCO_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCOBASE +03h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
10.9.4
Bit
Description
TCO Data Out Value — R/W. This data register field is used for passing commands
7:0
from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in
the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL
bits.
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +04h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Core
(Except bit 7, in RTC)
Bit
Description
15:13 Reserved
DMISERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
12 _{1 = Intel}^® _{ICH7 received a DMI special cycle message via DMI indicating that it wants}
to cause an SERR#. The software must read the (G)MCH to determine the reason
for the SERR#.
11 Reserved
DMISMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
10 _{1 = ICH7 received a DMI special cycle message via DMI indicating that it wants to}
cause an SMI. The software must read the (G)MCH to determine the reason for the
SMI.
DMISCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
9 _{1 = ICH7 received a DMI special cycle message via DMI indicating that it wants to}
cause an SCI. The software must read the (G)MCH to determine the reason for the
SCI.
Intel ^® ICH7 Family Datasheet
457