307013-003 Datasheet, PDF (355/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.19
BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh–3Fh
Default Value: 0000h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
15:12 Reserved
Discard Timer SERR# Enable (DTE) — R/W. Controls the generation of SERR# on
the primary interface in response to the DTS bit being set:
11
0 = Do not generate SERR# on a secondary timer discard
1 = Generate SERR# in response to a secondary timer discard
10
Discard Timer Status (DTS) — R/WC. This bit is set to 1 when the secondary discard
timer (see the SDT bit below) expires for a delayed transaction in the hard state.
Secondary Discard Timer (SDT) — R/W. This bit sets the maximum number of PCI
clock cycles that the Intel^® ICH7 waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed transaction data is has been
returned by the system and is in a buffer in the ICH7 PCI bridge. If the master has not
9
repeated the transaction at least once before the counter expires, the ICH7 PCI bridge
discards the transaction from its queue.
0 = The PCI master timeout value is between 2¹⁵ and 2¹⁶ PCI clocks
1 = The PCI master timeout value is between 2¹⁰ and 2¹¹ PCI clocks
8 Primary Discard Timer (PDT) — R/W. This bit is R/W for software compatibility only.
7
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The PCI logic will not generate
fast back-to-back cycles on the PCI bus.
Secondary Bus Reset (SBR) — R/W. This bit controls PCIRST# assertion on PCI.
0 = Bridge de-asserts PCIRST#
6 _{1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction}
buffers, posting buffers, and the PCI bus are initialized back to reset conditions.
The rest of the part and the configuration registers are not affected.
Master Abort Mode (MAM) — R/W. This bit controls the ICH7 PCI bridge’s behavior
when a master abort occurs:
Master Abort on (G)MCH/ICH7 Interconnect (DMI):
0 = Bridge asserts TRDY# on PCI. It drives all 1’s for reads, and discards data on
writes.
1 = Bridge returns a target abort on PCI.
5
Master Abort PCI (non-locked cycles):
0 = Normal completion status will be returned on the (G)MCH/ICH7 interconnect.
1 = Target abort completion status will be returned on the (G)MCH/ICH7 interconnect.
NOTE: All locked reads will return a completer abort completion status on the (G)MCH/
ICH7 interconnect.
VGA 16-Bit Decode (V16D) — R/W. This bit controls enables the ICH7 PCI bridge to
4 provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias
addresses every 1 KB. This bit requires the VGAE bit in this register be set.
Intel ^® ICH7 Family Datasheet
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