307013-003 Datasheet, PDF (197/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.17.7
Note:
5.18
5.18.1
Serial ATA Reference Clock Low Power Request
(SATACLKREQ#)
The 100 MHz Serial ATA Reference Clock (SATACLKP, SATACLKN) is implemented on the
system as a ground-terminated low-voltage differential signal pair driven by the system
Clock Chip. When all the SATA links are in Slumber or disabled, the SATA Reference
Clock is not needed and may be stopped and tri-stated at the clock chip allowing
system-level power reductions.
The ICH7 uses the SATACLKREQ# output signal to communicate with the system Clock
Chip to request either SATA clock running or to tell the system clock chip that it can
stop the SATA Reference Clock. ICH7 drives this signal low to request clock running,
and tristates the signal to indicate that the SATA Reference Clock may be stopped (the
ICH7 does not drive the pin high). When the SATACLKREQ# is tristated by the ICH7,
the clock chip may stop the SATA Reference Clock within 100 ns, anytime after 100 ns,
or not at all. If the SATA Reference Clock is not already running, it will start within 100
ns after a SATACLKREQ# is driven low by the ICH7.
To enable SATA Reference Clock Low Power Request:
1. Configure GPIO35 to native function
2. Set SATA Clock Request Enable (SCRE) bit to ‘1’ (Dev 31:F2:Offset 94h:bit 28).
The reset default for SATACLKREQ# is low to insure that the SATA Reference Clock is
running after system reset.
High Precision Event Timers
This function provides a set of timers that can be used by the operating system. The
timers are defined such that in the future, the operating system may be able to assign
specific timers to used directly by specific applications. Each timer can be configured to
cause a separate interrupt.
ICH7 provides three timers. The three timers are implemented as a single counter each
with its own comparator and value register. This counter increases monotonically. Each
individual timer can generate an interrupt when the value in its value register matches
the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system
(See Section 6.4). It is not expected that the operating system will move the location
of these timers once it is set by the BIOS.
Timer Accuracy
1. The timers are accurate over any 1 ms period to within 0.05% of the time specified
in the timer resolution fields.
2. Within any 100 microsecond period, the timer reports a time that is up to two ticks
too early or too late. Each tick is less than or equal to 100 ns, so this represents an
error of less than 0.2%.
3. The timer is monotonic. It does not return the same value on two consecutive
reads (unless the counter has rolled over and reached the same value).
Intel ^® ICH7 Family Datasheet
197