307013-003 Datasheet, PDF (503/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.24 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset: 4Ah–4Bh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Note:
This register is R/W to maintain software compatibility and enable parallel ATA
functionality when the PCI functions are combined. These bits have no effect on SATA
operation, unless otherwise noted.
Bit
Description
15:14 Reserved
13:12
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
00 = CT 4 clocks, RP 6
clocks
SCB1 = 1 (66 MHz clk)
00 = Reserved
FAST_SCB1 = 1
(133 MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 5
clocks
01 = CT 3 clocks, RP 8
clocks
01 = CT 3 clocks, RP 16
clocks
10 = CT 2 clocks, RP 4
clocks
10 = CT 2 clocks, RP 8
clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
11:10 Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of
these bits determines the minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these bits.
SCB1 = 0 (33 MHz clk) SCB1 = 1 (66 MHz clk)
FAST_SCB1 = 1
(133 MHz clk)
00 = CT 4 clocks, RP 6
9:8
clocks
00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5
clocks
01 = CT 3 clocks, RP 8
clocks
01 = CT 3 clocks, RP 16
clocks
10 = CT 2 clocks, RP 4
clocks
10 = CT 2 clocks, RP 8
clocks
10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
7:6 Reserved
Intel ^® ICH7 Family Datasheet
503