307013-003 Datasheet, PDF (477/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

UHCI Controllers Registers
Bit
Description
SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. This bit indicates if the event
occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this
bit will still be active. It is up to the SMM code to use the enable bit to determine the
8
exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI at End of Pass-Through Enable (SMIATENDPS) — R/W. This bit enables SMI
at the end of a pass-through. This can occur if an SMI is generated in the middle of a
7 ^{pass-through, and needs to be serviced later.}
0 = Disable
1 = Enable
Pass Through State (PSTATE) — RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to
6
0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through
sequence.
A20Gate Pass-Through Enable (A20PASSEN) — R/W.
0 = Disable.
5 _{1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence}
involving writes to port 60h and 64h does not result in the setting of the SMI status
bits.
SMI on USB IRQ Enable (USBSMIEN) — R/W.
4 0 = Disable
1 = Enable. USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN) — R/W.
3 _{0 = Disable}
1 = Enable. A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN) — R/W.
2 _{0 = Disable}
1 = Enable. A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN) — R/W.
1 0 = Disable
1 = Enable. A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN) — R/W.
0 _{0 = Disable}
1 = Enable. A 1 in bit 8 will cause an SMI event.
Intel ^® ICH7 Family Datasheet
477