307013-003 Datasheet, PDF (682/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
Bit
Description
Maximum Link Width (MLW) — RO. For the root ports, several values can be taken,
based upon the value of the chipset configuration register field RPC.PC1 (Chipset
Configuration Registers:Offset 0224h:bits1:0) for Ports 1–4 and RPC.PC2 (Chipset
Configuration Registers:Offset 0224h:bits1:0) for Ports 5 and 6.
Value of MLW Field
Port #
RPC.PC1=00b
RPC.PC1=11b
1
01h
04h
9:4
2
01h
01h
3
01h
01h
4
01h
01h
Port #
RPC.PC2=00b
RPC.PC2=11b
5
01h
N/A
6
01h
N/A
3:0 Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.
18.1.28 LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 50h-51h
Default Value: 0000h
Attribute:
Size:
R/W, WO, RO
16 bits
Bit
15:8
7
6
5
4
3
2
Description
Reserved
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
L1 prior to entering L0.
Common Clock Configuration (CCC) — R/W.
0 = The Intel^® ICH7 and device are not using a common reference clock.
1 = The ICH7 and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5:52, bit 11) to check the status
of training.
Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC) — RO. This bit indicates that the read
completion boundary is 64 bytes.
Reserved
682
Intel ^® ICH7 Family Datasheet