307013-003 Datasheet, PDF (416/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.7.2
Note:
Bit
Description
PCI SERR# Enable (PCI_SERR_EN) — R/W.
2 _{0 = SERR# NMIs are enabled.}
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable (SPKR_DAT_EN) — R/W.
1 _{0 = SPKR output is a 0.}
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0 _{0 = Disable}
1 = Enable
NMI_EN—NMI Enable (and Real Time Clock Index)
Register (LPC I/F—D31:F0)
I/O Address: 70h
Default Value: 80h
Lockable:
No
Attribute:
Size:
Power Well:
R/W (special)
8-bit
Core
The RTC Index field is write-only for normal operation. This field can only be read in Alt-
Access Mode. Note, however, that this register is aliased to Port 74h (documented in),
and all bits are readable at that address.
10.7.3
Bits
7
6:0
Description
NMI Enable (NMI_EN) — R/W (special).
0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX) — R/W (special). This data goes to
the RTC to select which register or CMOS RAM address is being accessed.
PORT92—Fast A20 and Init Register (LPC I/F—D31:F0)
I/O Address: 92h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
7:2 Reserved
Alternate A20 Gate (ALT_A20_GATE) — R/W. This bit is Or’d with the A20GATE
input signal to generate A20M# to the processor.
1
0 = A20M# signal can potentially go active.
1 = This bit is set when INIT# goes active.
0
INIT_NOW — R/W. When this bit transitions from a 0 to a 1, the Intel^® ICH7 will force
INIT# active for 16 PCI clocks.
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Intel ^® ICH7 Family Datasheet