307013-003 Datasheet, PDF (270/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.12
RCTCL—Root Complex Topology Capabilities List Register
Offset Address: 0100–0103h
Default Value: 1A010005h
Attribute:
Size:
RO
32-bit
7.1.13
Bit
31:20
19:16
15:0
Description
Next Capability (NEXT) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates the version of the capability
structure.
Capability ID (CID) — RO. This field indicates this is a PCI Express* link capability
section of an RCRB.
ESD—Element Self Description Register
Offset Address: 0104–0107h
Default Value: 00000602h
Attribute:
Size:
R/WO, RO
32-bit
7.1.14
Bit
31:24
23:16
15:8
7:4
3:0
Description
Port Number (PN) — RO. A value of 0 to indicate the egress port for the Intel^® ICH7.
Component ID (CID) — R/WO. This field indicates the component ID assigned to
this element by software. This is written once by platform BIOS and is locked until a
platform reset.
Number of Link Entries (NLE) — RO. This field indicates that one link entry
(corresponding to DMI), 6 root port entries (for the downstream ports), and the
Intel^® High Definition Audio device are described by this RCRB.
Reserved
Element Type (ET) — RO. This field indicates that the element type is a root complex
internal link.
ULD—Upstream Link Descriptor Register
Offset Address: 0110–0113h
Default Value: 00000001h
Attribute:
Size:
R/WO, RO
32-bit
Bit
31:24
23:16
15:2
1
0
Description
Target Port Number (PN) — R/WO. This field is programmed by platform BIOS to
match the port number of the (G)MCH RCRB that is attached to this RCRB.
Target Component ID (TCID) — R/WO. This field is programmed by platform BIOS
to match the component ID of the (G)MCH RCRB that is attached to this RCRB.
Reserved
Link Type (LT) — RO. This bit indicates that the link points to the (G)MCH RCRB.
Link Valid (LV) — RO. This bit indicates that the link entry is valid.
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Intel ^® ICH7 Family Datasheet