307013-003 Datasheet, PDF (235/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Figure 5-13. AC ’97 2.3 Controller-Codec Connection
Intel^®
ICH7
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
ACZ_BIT_CLK
ACZ_SDIN2
ACZ_SDIN1
ACZ_SDIN0
AC / MC / AMC
Primary Codec
AC / MC / AMC
Secondary Codec
AC / MC / AMC
Tertiary Codec
AC97 ICH codec conn
ICH7 core well outputs may be used as strapping options for the ICH7, sampled during
system reset. These signals may have weak pullups/pulldowns; however, this will not
interfere with link operation. ICH7 inputs integrate weak pulldowns to prevent floating
traces when a secondary and/or tertiary codec is not attached. When the Shut Off bit in
the control register is set, all buffers will be turned off and the pins will be held in a
steady state, based on these pullups/pulldowns.
ACZ_BIT_CLK is fixed at 12.288 MHz and is sourced by the primary codec. It provides
the necessary clocking to support the twelve 20-bit time slots. AC-link serial data is
transitioned on each rising edge of ACZ_BIT_CLK. The receiver of AC-link data samples
each serial bit on the falling edge of ACZ_BIT_CLK.
If ACZ_BIT_CLK makes no transitions for four consecutive PCI clocks, the ICH7
assumes the primary codec is not present or not working. It sets bit 28 of the Global
Status Register
(I/O offset 30h). All accesses to codec registers with this bit set will return data of FFh
to prevent system hangs.
Intel ^® ICH7 Family Datasheet
235