307013-003 Datasheet, PDF (643/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Bit
Description
AD3 — R/W. Power down semaphore for Audio. This bit exists in the suspend well and
maintains context across power states (except G3). The bit has no hardware function.
16
It is used by software in conjunction with the MD3 bit to coordinate the entry of the two
codecs into D3 state.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read
completions.
0 = A codec read completes normally.
15 _{1 = A codec read results in a time-out. The bit remains set until being cleared by}
software writing a 1 to the bit location.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
14 Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.
13 Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.
12 Bit 1 of slot 12 — RO. Display bit 1 of the most recent slot 12.
ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.
11 ^{0 = Resume event did Not occur}
1 = Resume event occurred.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
ACZ_SDIN1 Resume Interrupt (S1R1) — R/WC. This bit indicates that a resume
event occurred on ACZ_SDIN1. Software clears this bit by writing a 1 to it.
10 ^{0 = Resume event did Not occur}
1 = Resume event occurred.
NOTE: This bit is not affected by D3_HOT to D0 Reset.
ACZ_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in
ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software
must check this bit before starting the bus masters. Once the codec is “ready”, it must
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not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
ACZ_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in
ACZ_SDIN0. Bus masters ignore the condition of the codec ready bits, so software
must check this bit before starting the bus masters. Once the codec is “ready”, it must
8
not go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Microphone In Interrupt (MINT) — RO.
7 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
6 0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
5 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the PCM in channel interrupts status bits has been set.
4:3 Reserved
Intel ^® ICH7 Family Datasheet
643