307013-003 Datasheet, PDF (88/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
Table 3-4. Power Plane and States for Output and I/O Signals for Mobile/Ultra Mobile
Only Configurations (Sheet 3 of 4)
Signal Name
Power
Plane
During
PLTRST#¹ /
RSMRST#²
Immediately
after
PLTRST#¹ /
RSMRST#²
C3/C4
S1
S3_COLD3
S4/
S5
A20M#
CPUPWRGD /
GPIO49
IGNNE#
INIT#
INIT3_3V#
INTR
NMI
SMI#
STPCLK#
DPSLP#
SMBCLK,
SMBDATA
SMLINK[1:0]
LINKALERT#
SPKR
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_SYNC
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Processor Interface
Dependant
on A20GATE
Signal
See Note 8
Defined
See Note 9
High
High
High
See Note 8
High
High
High
High
See Note 10 See Note 10
See Note 10 See Note 10
High
High
High
High
High
High
SMBus Interface
High
High
High
Defined
Defined
Defined
Low
High/Low
High
High
High
High
High
Low
Low
High
Low
High
Suspend
High-Z
High-Z
Defined Defined
System Management Interface
Suspend
High-Z
High-Z
Defined Defined
Suspend
High-Z
High-Z
Defined Defined
Miscellaneous Signals
Core
High-Z with
Internal Pull-
down
Low
Defined Defined
AC ’97 Interface (Mobile Only)
Suspend
Core
Core
Suspend
Core
Core
Low
Low
High
Low
Running
Running
Low
Running
Running
Intel^® High Definition Audio Interface
Low
Low¹¹
High
High-Z with
Internal Pull-
down
Running
Running
High-Z with
Internal Pull-
down
Running
Running
Cold
Reset Bit
(High)
Low
Low
TBD
Low
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Defined
Defined
Defined
Off
Low
Off
Off
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Define
d
Define
d
Define
d
Off
Low
Off
Off
Low
Off
Off
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Intel ^® ICH7 Family Datasheet