307013-003 Datasheet, PDF (83/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
Table 3-3. Power Plane and States for Output and I/O Signals for Desktop Only
Configurations (Sheet 3 of 5)
Signal Name
Power
Plane
During
PLTRST#¹ /
RSMRST#²
Immediately
after
PLTRST#¹ /
RSMRST#²
S1
S3_COLD3
SATARBIAS
SATA3GP / GPIO37
SATA2GP / GPIO36
SATA1GP / GPIO19
SATA0GP / GPIO21
SATACLKREQ# /
GPIO35
Core
Core
Core
High-Z
Input
Low
High-Z
Input
High-Z
Off
Driven
Driven
Low
Defined
Off
Interrupts
PIRQ[A:D]#,
PIRQ[H:E]# /
GPIO[5:2]
SERIRQ
Core
Core
High-Z
High-Z
High-Z
High-Z
High-Z
Off
High-Z
Off
USB Interface
USBP[7:0][P,N]
USBRBIAS
OC[7:5]# /
GPIO[31:29]
Suspend
Suspend
Suspend
Low
High-Z
Input
Low
High-Z
Input
Low
Defined
Driven
Low
Defined
Driven
Power Management
PLTRST#
SLP_S3#
SLP_S4#
SLP_S5#
SUS_STAT#
SUSCLK
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Low
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High
High
High
Running
Low
Low
High
High
Low
Processor Interface
A20M#
CPUPWRGD /
GPIO49
CPUSLP#
IGNNE#
INIT#
INIT3_3V#
INTR
NMI
SMI#
Dependant
Core
on A20GATE See Note 6
High
Off
Signal
Core
Defined
High⁷
High
Off
Core
High
High
Defined
Off
Core
High
See Note 6
High
Off
Core
High
High
High
Off
Core
High
High
High
Off
Core
See Note 6
See Note 8
Low
Off
Core
See Note 6
See Note 8
Low
Off
Core
High
High
High
Off
S4/S5
Off
Driven
Off
Off
Off
Low
Defined
Driven
Low
Low
Low
Low⁵
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Intel ^® ICH7 Family Datasheet
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