307013-003 Datasheet, PDF (728/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2
Intel^® High Definition Audio Memory-Mapped
Configuration Registers
(Intel^® High Definition Audio— D27:F0)
The base memory location for these memory mapped configuration registers is
specified in the HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The
individual registers are then accessible at HDBAR + Offset as indicated in the following
table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 19-2. Intel^® High Definition Audio PCI Register Address Map
(Intel^® High Definition Audio D27:F0) (Sheet 1 of 4)
HDBAR +
Offset
00h–01h
02h
03h
04h–05h
06h–07h
08h–0Bh
0Ch–0Dh
0Eh–0Fh
10h–11h
12h–13h
14h–17h
1 8h–19h
1Ah–1Bh
1Ch–1Fh
20h–23h
24h–27h
30h–33h
34h–37h
40h–43h
44h–47h
48h–49h
4Ah–4Bh
4Ch
4Dh
4Eh
50h–53h
54h–57h
Mnemonic
Register Name
GCAP
Global Capabilities
VMIN
Minor Version
VMAJ
Major Version
OUTPAY Output Payload Capability
INPAY
Input Payload Capability
GCTL
Global Control
WAKEEN Wake Enable
STATESTS State Change Status
GSTS
Global Status
—
Reserved
ECAP
Extended Capabilities (Mobile/Ultra
Mobile Only)
OUTSTRMPAY Output Stream Payload Capability
INSTRMPAY Input Stream Payload Capability
—
Reserved
INTCTL
Interrupt Control
INTSTS
Interrupt Status
WALCLK Wall Clock Counter
SSYNC
Stream Synchronization
CORBLBASE CORB Lower Base Address
CORBUBASE CORB Upper Base Address
CORBWP CORB Write Pointer
CORBRP CORB Read Pointer
CORBCTL CORB Control
CORBST CORB Status
CORBSIZE CORB Size
RIRBLBASE RIRB Lower Base Address
RIRBUBASE RIRB Upper Base Address
Default
Access
4401h
00h
01h
003Ch
001Dh
00000000h
0000h
0000h
0000h
0000h
RO
RO
RO
RO
RO
R/W
R/W
R/WC
R/WC
RO
00000001h
RO
0030h
0018h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
0000h
0000h
00h
00h
42h
00000000h
00000000h
RO
RO
RO
R/W
RO
RO
R/W
R/W, RO
R/W
R/W
R/W
R/W
R/WC
RO
R/W, RO
R/W
728
Intel ^® ICH7 Family Datasheet