307013-003 Datasheet, PDF (522/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.2.3
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset: Primary: BAR + 04h–07h Attribute:
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined
Size:
R/W
32 bits
12.2.4
Bit
31:2
1:0
Description
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to
A[31:2]. The Descriptor Table must be DWord-aligned. The Descriptor Table must not
cross a 64-K boundary in memory.
Reserved
AIR—AHCI Index Register (D31:F2)
Address Offset: Primary: BAR + 10h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
12.2.5
Bit
Description
31:10 Reserved
Index (INDEX)— R/W: This Index register is used to select the DWord offset of the
9:2 Memory Mapped AHCI register to be accessed. A DWord, Word or Byte access is
specified by the active byte enables of the I/O access to the Data register.
1:0 Reserved
AIDR—AHCI Index Data Register (D31:F2)
Address Offset: Primary: BAR + 14h
Default Value: All bits undefined
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Data (DATA)— R/W: This Data register is a “window” through which data is read or
written to the AHCI memory mapped registers. A read or write to this Data register
triggers a corresponding read or write to the memory mapped register pointed to by
the Index register. The Index register must be setup prior to the read or write to this
Data register.
Note that a physical register is not actually implemented as the data is actually stored
in the memory mapped registers.
Since this is not a physical register, the “default” value is the same as the default value
of the register pointed to by Index.
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Intel ^® ICH7 Family Datasheet