307013-003 Datasheet, PDF (723/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.39 PVCCTL — Port VC Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 10Ch–10Dh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:4
3:1
0
Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However,
these bits are not applicable since the Intel^® High Definition Audio controller reports a 0
in the Low Priority Extended VC Count bits in the PVCCAP1 register.
Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not
present.
19.1.40 PVCSTS—Port VC Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 10Eh-10Fh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:1 Reserved.
0
VC Arbitration Table Status — RO. Hardwired to 0 since an arbitration table is not
present.
19.1.41 VC0CAP—VC0 Resource Capability Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 110h–113h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
Port Arbitration Table Offset — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
23 Reserved.
22:16
Maximum Time Slots — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
15
Reject Snoop Transactions — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
14
Advanced Packet Switching — RO. Hardwired to 0 since this field is not valid for
endpoint devices.
13:8 Reserved.
7:0
Port Arbitration Capability — RO. Hardwired to 0 since this field is not valid for endpoint
devices.
Intel ^® ICH7 Family Datasheet
723