307013-003 Datasheet, PDF (120/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.5.1.3
Cycle Type / Direction (CYCTYPE + DIR)
The ICH7 drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0. Table 5-7 shows the valid bit encodings.
Table 5-7.
Cycle Type Bit Definitions
Bits[3:2] Bit1
Definition
00
0
I/O Read
00
1
I/O Write
Desktop and Mobile: DMA Read
10
0
Ultra Mobile: Reserved
Desktop and Mobile: DMA Write
10
1
Ultra Mobile: Reserved
11
x
Reserved. If a peripheral performing a bus master cycle generates this
value, the Intel^® ICH7 aborts the cycle.
NOTE: All other encodings are RESERVED.
5.5.1.4
SIZE
Bits[3:2] are reserved. The ICH7 drives them to 00. Peripherals running bus master
cycles are also supposed to drive 00 for bits 3:2; however, the ICH7 ignores those bits.
Bits[1:0] are encoded as listed in Table 5-8.
Table 5-8.
Transfer Size Bit Definition
Bits[1:0]
Size
00
8-bit transfer (1 byte)
01
16-bit transfer (2 bytes)
Reserved. The Intel^® ICH7 does not drive this combination. If a peripheral
10
running a bus master cycle drives this combination, the ICH7 may abort the
transfer.
11
32-bit transfer (4 bytes)
120
Intel ^® ICH7 Family Datasheet