307013-003 Datasheet, PDF (750/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.36 SDCTL—Stream Descriptor Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 80h
Input Stream[1]: HDBAR + A0h
Input Stream[2]: HDBAR + C0h
Input Stream[3]: HDBAR + E0h
Output Stream[0]: HDBAR + 100h
Output Stream[1]: HDBAR + 120h
Output Stream[2]: HDBAR + 140h
Output Stream[3]: HDBAR + 160h
Attribute:
R/W, RO
Default Value: 040000h
Size: 24 bits
Bit
Description
23:20
19
18
(Desktop
and Mobile
Only)
18
(Ultra
Mobile
Only)
17:16
15:5
4
3
Stream Number — R/W. This value reflects the Tag associated with the data
being transferred on the link.
When data controlled by this descriptor is sent out over the link, it will have its
stream number encoded on the SYNC signal.
When an input stream is detected on any of the SDI signals that match this value,
the data samples are loaded into FIFO associated with this descriptor.
Note that while a single SDI input may contain data from more than one stream
number, two different SDI inputs may not be configured with the same stream
number.
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control — RO. This bit is only meaningful for bidirectional
streams; therefore, this bit is hardwired to 0.
Traffic Priority — RO. Hardwired to 1 indicating that all streams will use VC1 if it is
enabled through the PCI Express* registers.
Reserved
Stripe Control — RO. This bit is only meaningful for input streams; therefore, this
bit is hardwired to 0.
Reserved
Descriptor Error Interrupt Enable — R/W.
0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable — R/W.
0 = Disable.
1 = Enable. This bit controls whether the occurrence of a FIFO error (overrun for
input or underrun for output) will cause an interrupt or not. If this bit is not
set, bit 3 in the Status register will be set, but the interrupt will not occur.
Either way, the samples will be dropped.
750
Intel ^® ICH7 Family Datasheet