307013-003 Datasheet, PDF (439/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.6
LV2 — Level 2 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 14h
(ACPI P_BLK+4)
00h
No
Core
Attribute:
Size:
Usage:
RO
8-bit
ACPI or Legacy
10.8.3.7
10.8.3.8
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
7:0
register generate a “enter a level 2 power state” (C2) to the clock control logic. This will
cause the STPCLK# signal to go active, and stay active until a break event occurs.
Throttling (due either to THTL_EN or FORCE_THTL) will be ignored.
NOTE: This register should not be used by Intel^® iA64 processors or systems with more than 1
logical processor, unless appropriate semaphoring software has been put in place to ensure
that all threads/processors are ready for the C2 state when the “read to this register”
instruction occurs.
LV3—Level 3 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
PMBASE + 15h (ACPI P_BLK + 5)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
7:0 register generate a “enter a C3 power state” to the clock control logic. The C3 state
persists until a break event occurs.
NOTE: If the C4onC3_EN bit is set, reads this register will initiate a LVL4 transition rather than a
LVL3 transition. In the event that software attempts to simultaneously read the LVL2 and
LVL3 registers (which is not permitted), the Intel^® ICH7-M/ICH7-U will ignore the LVL3
read, and only perform a C2 transition.
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C3 state when the “read to this register”
instruction occurs.
LV4—Level 4 Register (Mobile/Ultra Mobile Only)
I/O Address:
Default Value:
Lockable:
PMBASE + 16h (ACPI P_BLK + 6)
Attribute:
00h
Size:
No
Usage:
Power Well:
RO
8-bit
ACPI or Legacy
Core
Bit
Description
Reads to this register return all 0s, writes to this register have no effect. Reads to this
7:0 register generate a “enter a C4 power state” to the clock control logic. The C4 state
persists until a break event occurs.
NOTE: This register should not be used by iA64 processors or systems with more than 1 logical
processor, unless appropriate semaphoring software has been put in place to ensure that
all threads/processors are ready for the C4 state when the “read to this register”
instruction occurs.
Intel ^® ICH7 Family Datasheet
439