307013-003 Datasheet, PDF (323/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.8
Note:
8.2.9
EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0)
Offset Address: 18h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
The Early Receive Interrupt register allows the internal LAN controller to generate an
early interrupt depending on the length of the frame. The LAN controller will generate
an interrupt at the end of the frame regardless of whether or not Early Receive
Interrupts are enabled.
It is recommended that software not use this register unless receive interrupt latency
is a critical performance issue in that particular software environment. Using this
feature may reduce receive interrupt latency, but will also result in the generation of
more interrupts, which can degrade system efficiency and performance in some
environments.
Bit
Description
Early Receive Count — R/W. When some non-zero value x is programmed into this
register, the LAN controller will set the ER bit in the SCB Status Word Register and assert
7:0
INTA# when the byte count indicates that there are x qwords remaining to be received
in the current frame (based on the Type/Length field of the received frame). No Early
Receive interrupt will be generated if a value of 00h (the default value) is programmed
into this register.
FLOW_CNTL—Flow Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 19h–1Ah
Default Value: 0000h
Attribute:
Size:
RO, R/W (special)
16 bits
Bit
Description
15:13 Reserved
FC Paused Low — RO.
12 ^{0 = Cleared when the FC timer reaches 0, or a Pause frame is received.}
1 = Set when the LAN controller receives a Pause Low command with a value greater
than 0.
FC Paused — RO.
0 = Cleared when the FC timer reaches 0.
11 1 = Set when the LAN controller receives a Pause command regardless of its cause
(FIFO reaching Flow Control Threshold, fetching a Receive Frame Descriptor with its
Flow Control Pause bit set, or software writing a 1 to the Xoff bit).
FC Full — RO.
10 _{0 = Cleared when the FC timer reaches 0.}
1 = Set when the LAN controller sends a Pause command with a value greater than 0.
Xoff — R/W (special). This bit should only be used if the LAN controller is configured to
operate with IEEE frame-based flow control.
9 ^{0 = This bit can only be cleared by writing a 1 to the Xon bit (bit 8 in this register).}
1 = Writing a 1 to this bit forces the Xoff request to 1 and causes the LAN controller to
behave as if the FIFO extender is full. This bit will also be set to 1 when an Xoff
request due to an “RFD Xoff” bit.
Intel ^® ICH7 Family Datasheet
323