307013-003 Datasheet, PDF (824/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Figure 23-18. Power Sequencing and Reset Signal Timings (Desktop Only)
PWROK
V_CPU_IO
Vcc1_5_A,
Vcc1_5_B
Vcc1_05
and other
power¹
Vcc3_3
V5REF
LAN_RST#,
RSMRST#
VccSus1_05
VccSus3_3
V5REF_Sus
t214
t213
t211
t209
t203
t204
t202
t201
RTCRST#
VccRTC
t200
ICH7 P S D kt
d
NOTES:
1.
Other power includes VccUSBPLL, VccDMIPLL, and VccSATAPLL. All of these power signals
must independently meet the timings shown in the figure. There are no timing
interdependencies between Vcc1_05 and these other power signals. There are also no
timing interdependencies for these power signals, including Vcc1_05, to Vcc3_3 and
Vcc1_5_A/Vcc1_5_B. However, If Vcc3_3 (core well buffer) is powered before Vcc1_05
(core well logic), core well signal states are indeterminate, undefined, and may glitch prior
to PWROK assertion. Refer to Section 3.3 and Section 3.4 for a list of signals that will be
determinate before PWROK.
2.
PRWOK must not glitch, even if RSMRST# is low.
824
Intel ^® ICH7 Family Datasheet