307013-003 Datasheet, PDF (13/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0).......................................... 347
9.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)............................ 349
9.1.6 CC—Class Code Register (PCI-PCI—D30:F0) ............................................ 349
9.1.7 PMLT—Primary Master Latency Timer Register (PCI-PCI—D30:F0) ............... 350
9.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0) ................................. 350
9.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0) ...................................... 350
9.1.10 SMLT—Secondary Master Latency Timer Register (PCI-PCI—D30:F0) ........... 351
9.1.11 IOBASE_LIMIT—I/O Base and Limit Register (PCI-PCI—D30:F0) ................. 351
9.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0) ............................ 352
9.1.13 MEMBASE_LIMIT—Memory Base and Limit Register (PCI-PCI—D30:F0)........ 353
9.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
and Limit Register (PCI-PCI—D30:F0) ..................................................... 353
9.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................... 354
9.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI-PCI—D30:F0) ................................................................... 354
9.1.17 CAPP—Capability List Pointer Register (PCI-PCI—D30:F0) .......................... 354
9.1.18 INTR—Interrupt Information Register (PCI-PCI—D30:F0) ........................... 354
9.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)................................... 355
9.1.20 SPDH—Secondary PCI Device Hiding Register (PCI-PCI—D30:F0)................ 356
9.1.21 DTC—Delayed Transaction Control Register (PCI-PCI—D30:F0) ................... 357
9.1.22 BPS—Bridge Proprietary Status Register (PCI-PCI—D30:F0) ....................... 359
9.1.23 BPC—Bridge Policy Configuration Register (PCI-PCI—D30:F0)..................... 360
9.1.24 SVCAP—Subsystem Vendor Capability Register (PCI-PCI—D30:F0).............. 361
9.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)......................... 361
10 LPC Interface Bridge Registers (D31:F0) ............................................................... 363
10.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 363
10.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) .............................. 364
10.1.2 DID—Device Identification Register (LPC I/F—D31:F0) .............................. 364
10.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ................................ 365
10.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ....................................... 365
10.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ............................ 366
10.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................. 366
10.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) ..................................... 367
10.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0).................................... 367
10.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ............................ 367
10.1.10HEADTYP—Header Type Register (LPC I/F—D31:F0) .................................. 367
10.1.11SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................. 368
10.1.12CAPP—Capability List Pointer (LPC I/F—D31:F0) ....................................... 368
10.1.13PMBASE—ACPI Base Address Register (LPC I/F—D31:F0) .......................... 368
10.1.14ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ............................. 369
10.1.15GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ..................... 369
10.1.16GC—GPIO Control Register (LPC I/F — D31:F0) ........................................ 370
10.1.17PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) (Desktop and Mobile Only) .......................................... 370
10.1.18SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ....................... 371
10.1.19PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0) ................................................................................ 372
10.1.20LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0) .................. 373
10.1.21LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)................................ 374
10.1.22GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) .... 375
10.1.23GEN2_DEC—LPC I/F Generic Decode Range 2Register (LPC I/F—D31:F0)..... 375
10.1.24GEN3_DEC—LPC I/F Generic Decode Range 3Register (LPC I/F—D31:F0)..... 376
10.1.25GEN4_DEC—LPC I/F Generic Decode Range 4Register (LPC I/F—D31:F0)..... 376
10.1.26FWH_SEL1—Firmware Hub Select 1 Register (LPC I/F—D31:F0) ................. 377
Intel ^® ICH7 Family Datasheet
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