307013-003 Datasheet, PDF (282/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.40
TCTL—TCO Configuration Register
Offset Address: 3000–3000h
Default Value: 00h
Attribute:
Size:
R/W
8-bit
Bit
Description
TCO IRQ Enable (IE) — R/W.
7
0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
6:3 Reserved
TCO IRQ Select (IS) — R/W. Specifies on which IRQ the TCO will internally appear.
If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that
interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI
interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and
can be shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
011 = Reserved
2:0 _{100 = IRQ 20 (only if APIC enabled)}
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
NOTE: When setting the these bits, the IE bit should be cleared to prevent glitching.
NOTE: When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should
be programmed for active-high reception. When the interrupt is mapped to
APIC interrupts 20 through 23, the APIC should be programmed for active-
low reception.
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Intel ^® ICH7 Family Datasheet