307013-003 Datasheet, PDF (432/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Table 10-11. ACPI and Legacy I/O Register Map (Sheet 2 of 2)
PMBASE
+ Offset
Mnemonic
Register Name
ACPI Pointer
50h
—
Reserved (Desktop Only)
Intel SpeedStep^®
50h
SS_CNT
Technology Control
(Mobile/Ultra Mobile
Only)
51h–5Fh
—
Reserved
—
54h–57h
C3_RES
C3-Residency Register
(Mobile/Ultra Mobile
—
Only)
60h–7Fh
—
Reserved for TCO
—
Default
Type
01h
R/W (special)
—
—
00000000h RO, R/W
—
—
10.8.3.1
Note:
PM1_STS—Power Management 1 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Bits 0–7: Core,
Bits 8–15: Resume,
except Bit 11 in RTC
Attribute:
Size:
Usage:
R/WC
16-bit
ACPI or Legacy
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then the ICH7 will generate a Wake Event. Once back in an S0 state (or if
already in an S0 state when the event occurs), the ICH7 will also generate an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.
Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
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Intel ^® ICH7 Family Datasheet