307013-003 Datasheet, PDF (340/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.17
8.3.18
RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0)
Offset Address: F4h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is a means for software to read the current sequence number that
hardware is using in RMCP packets. Software can also change the value. Software
should only write to this register while the GLOBAL ENABLE is off.
Bit
Description
RMCP Sequence Number (RSEQ_VAL) — R/W. This is the current sequence number
of the RMCP packet being sent or the sequence number of the next RMCP packet to be
7:0
sent. This value can be set by software. At reset, it defaults to 00h. If the sequence
number is not FFh, the ASF controller will automatically increment this number by one
(or rollover to 00h if incrementing from FEh) after a successful RMCP packet
transmission.
SP_MODE—Special Modes Register
(ASF Controller—B1:D8:F0)
Offset Address: F5h
Default Value: x0h
Attribute:
Size:
The register contains miscellaneous functions.
R/WC, RO
8 bits
8.3.19
Bit
Description
SMBus Activity Bit (SPE_ACT) — RO.
7 1 = ASF controller is active with a SMBus transaction. This is an indicator to software
that the ASF controller is still processing commands on the SMBus.
Watchdog Status (SPE_WDG) — R/WC.
6 _{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set when a watchdog expiration occurs.
Link Loss Status (SPE_LNK) — R/WC.
5 0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a link loss occurs (link is down for more than 5 seconds).
4:0 Reserved
INPOLL_TCONF—Inter-Poll Timer Configuration Register
(ASF Controller—B1:D8:F0)
Offset Address: F6h
Default Value: 10h
Attribute:
Size:
R/W
8 bits
This register is used to load and hold the value (in increments of 5 ms) for the polling
timer. This value determines how often the ASF polling timer expires which determines
the minimum idle time between sensor polls.
Bit
Description
Inter-Poll Timer Configuration (IPTC_VAL) — R/W. This field identifies the time, in
7:0 5.24 ms units that the ASF controller will wait between the end of the one ASF Poll Alert
Message to start on the next. The value 00h is invalid and unsupported.
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Intel ^® ICH7 Family Datasheet