307013-003 Datasheet, PDF (401/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.4.9
OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Master Controller – 020h Attribute:
Slave Controller – 0A0h Size:
Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
WO
8 bits
Bit
Description
7 Reserved. Must be 0.
Special Mask Mode (SMM) — WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically
6
alter the system priority structure while the routine is executing, through selective
enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be
set for this bit to have any meaning.
Enable Special Mask Mode (ESMM) — WO.
5 _{0 = Disable. The SMM bit becomes a “don't care”.}
1 = Enable the SMM bit to set or reset the Special Mask Mode.
4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command — WO.
0 = Disable. Poll Command is not issued.
2 _{1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt}
acknowledge cycle. An encoded byte is driven onto the data bus, representing the
highest priority level requesting service.
Register Read Command — WO. These bits provide control for reading the In-Service
Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not
affect the register read selection. When bit 1=1, bit 0 selects the register status
returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR
will be read. Following ICW initialization, the default OCW3 port address read will be
“read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to
1:0 ^{bit 1 when programming this register. The selected register can be read repeatedly}
without reprogramming OCW3. To select a new status register, OCW3 must be
reprogrammed prior to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
Intel ^® ICH7 Family Datasheet
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