307013-003 Datasheet, PDF (189/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.16.3.1
Operation
Initial setup programming consists of enabling and performing the proper configuration
of the ICH7 and the IDE device for Ultra ATA/100/66/33 operation. For the ICH7, this
consists of enabling synchronous DMA mode and setting up appropriate Synchronous
DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE
programming model is followed. Once programmed, the drive and ICH7 control the
transfer of data via the Ultra ATA/100/66/33 protocol. The actual data transfer consists
of three phases, a start-up phase, a data transfer phase, and a burst termination
phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to
begin the transfer, the ICH7 asserts DMACK# signal. When DMACK# signal is asserted,
the host controller drives CS0# and CS1# inactive, DA0–DA2 low. For write cycles, the
ICH7 deasserts STOP, waits for the IDE device to assert DMARDY#, and then drives the
first data word and STROBE signal. For read cycles, the ICH7 tri-states the DD lines,
deasserts STOP, and asserts DMARDY#. The IDE device then sends the first data word
and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (ICH7 –
writes, IDE device – reads) providing data and toggling STROBE. Data is transferred
(latched by receiver) on each rising and falling edge of STROBE. The transmitter can
pause the burst by holding STROBE high or low, resuming the burst by again toggling
STROBE. The receiver can pause the burst by deasserting DMARDY# and resumes the
transfers by asserting DMARDY#. The ICH7 pauses a burst transaction to prevent an
internal line buffer over or under flow condition, resuming once the condition has
cleared. It may also pause a transaction if the current PRD byte count has expired,
resuming once it has fetched the next PRD.
The current burst can be terminated by either the transmitter or receiver. A burst
termination consists of a Stop Request, Stop Acknowledge and transfer of CRC data.
The ICH7 can stop a burst by asserting STOP, with the IDE device acknowledging by
deasserting DMARQ. The IDE device stops a burst by deasserting DMARQ and the ICH7
acknowledges by asserting STOP. The transmitter then drives the STROBE signal to a
high level. The ICH7 then drives the CRC value onto the DD lines and deassert
DMACK#. The IDE device latches the CRC value on rising edge of DMACK#. The ICH7
terminates a burst transfer if it needs to service the opposite IDE channel, if a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running the
burst, or upon transferring the last data from the final PRD.
Intel ^® ICH7 Family Datasheet
189