307013-003 Datasheet, PDF (436/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.3
PM1_CNT—Power Management 1 Control
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 04h
(ACPI PM1a_CNT_BLK)
00000000h
No
Bits 0–7: Core,
Bits 8–12: RTC,
Bits 13–15: Resume
Attribute:
Size:
Usage:
R/W, WO
32-bit
ACPI or Legacy
Bit
31:14
13
Description
Reserved.
Sleep Enable (SLP_EN) — WO. Setting this bit causes the system to sequence into
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP) — R/W. This 3-bit field defines the type of Sleep the system
should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
12:10
Code
000b
001b
010b
011b
100b
101b
110b
9:3 Reserved.
Master Interrupt
ON: Typically maps to S0 state.
Asserts STPCLK#. Puts processor in Stop-Grant state. Optional to
assert CPUSLP# to put processor in sleep state: Typically, maps to S1
state.
Reserved
Reserved
Reserved
Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to
S4 state.
Soft Off Assert SLP S3# SLP S4# and SLP S5#: Typically maps to
Global Release (GBL_RLS) — WO.
0 = This bit always reads as 0.
2
1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
has a corresponding enable and status bits to control its ability to receive ACPI
events.
1
(Desktop Reserved
Only)
1
(Mobile/
Ultra
Mobile
Only)
Bus Master Reload (BM_RLD) — R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 = Enable Bus Master requests (internal, external or BM_BUSY#) to cause a break
from the C3 state.
If software fails to set this bit before going to C3 state, the Intel^® ICH7-M/ICH7-U will
still return to a snoopable state from C3 or C4 states due to bus master activity.
SCI Enable (SCI_EN) — R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
0
GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
436
Intel ^® ICH7 Family Datasheet