307013-003 Datasheet, PDF (635/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.2.1
x_BDBAR—Buffer Descriptor Base Address Register
(Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
Size:
No
Power Well:
R/W
32 bits
Core
Software can read the register at offset 00h by performing a single 32-bit read from
address offset 00h. Reads across DWord boundaries are not supported.
16.2.2
Bit
Description
31:3
2:0
Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits
31:3. The data should be aligned on 8-byte boundaries. Each buffer descriptor is 8
bytes long and the list can contain a maximum of 32 entries.
Hardwired to 0.
x_CIV—Current Index Value Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 04h (PICIV), Attribute:
NABMBAR + 14h (POCIV),
NABMBAR + 24h (MCCIV)
MBBAR + 44h (MC2CIV)
MBBAR + 54h (PI2CIV)
MBBAR + 64h (SPCIV)
00h
Size:
No
Power Well:
RO
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 8-bit read to offset 04h.
Bit
Description
7:5 Hardwired to 0
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within
4:0 the list of 32 descriptors is currently being processed. As each descriptor is processed,
this value is incremented. The value rolls over after it reaches 31.
NOTE: Reads across DWord boundaries are not supported.
Intel ^® ICH7 Family Datasheet
635