307013-003 Datasheet, PDF (495/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.7
SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
Sub Class Code (SCC)
This field specifies the sub-class code of the controller, per the table below:
Intel^® ICH7 Desktop Only:
SCC Register Attribute
Scc Register Value
RO
01h (IDE Controller)
ICH7-M Only:
MAP.SMS
(D31:F2:Offset 90h:bit 7:6)
7:0
00b
01b
SCC Register Value
01h (IDE Controller)
06h (AHCI Controller)
Intel^® Matrix Storage Technology Enabled ICH7 components Only (ICH7R,
ICH7DH, and ICH7-M DH):
MAP.SMS
(D31:F2:Offset 90h:bit 7:6)
SCC Register Value
00b
01h (IDE Controller)
01b
06h (AHCI Controller)
10b
04h (RAID Controller)
12.1.8
BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2)
Address Offset: 0Bh
Default Value: 01h
Attribute:
Size:
RO
8 bits
12.1.9
Bit
Base Class Code (BCC) — RO.
7:0
01h = Mass storage device
Description
PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Master Latency Timer Count (MLTC) — RO.
7:0 _{00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated}
as a PCI device, so it does not need a Master Latency Timer.
Intel ^® ICH7 Family Datasheet
495