307013-003 Datasheet, PDF (166/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-33. Transitions Due to Power Failure
State at Power Failure AFTERG3_EN bit
S0, S1, S3
1
0
S4
1
0
S5
1
0
Transition When Power Returns
S5
S0
S4
S0
S5
S0
5.14.8
Thermal Management
The ICH7 has mechanisms to assist with managing thermal problems in the system.
5.14.8.1
Note:
THRM# Signal
The THRM# signal is used as a status input for a thermal sensor. Based on the THRM#
signal going active, the ICH7 generates an SMI# or SCI (depending on SCI_EN).
If the THRM_POL bit is set low, when the THRM# signal goes low, the THRM_STS bit
will be set. This is an indicator that the thermal threshold has been exceeded. If the
THRM_EN bit is set, then when THRM_STS goes active, either an SMI# or SCI will be
generated (depending on the SCI_EN bit being set).
The power management software (BIOS or ACPI) can then take measures to start
reducing the temperature. Examples include shutting off unwanted subsystems, or
halting the processor.
By setting the THRM_POL bit to high, another SMI# or SCI can optionally be generated
when the THRM# signal goes back high. This allows the software (BIOS or ACPI) to
turn off the cooling methods.
THRM# assertion does not cause a TCO event message in S3 or S4. The level of the
signal is not reported in the heartbeat message.
5.14.8.2
Processor Initiated Passive Cooling
This mode is initiated by software setting the THTL_EN (PMBASE+10h:bit 4) or
FORCE_THTL (PMBASE+10h:bit 8) bits.
Software sets the THTL_DTY (PMBASE+10h:bits 3:1) or THRM_DTY (PMBASE+10h:bits
7:5) bits to select throttle ratio and THTL_EN or FORCE_THTL bits to enable the
throttling.
Throttling results in STPCLK# active for a minimum time of 12.5% and a maximum of
87.5%. The period is 1024 PCI clocks. Thus, the STPCLK# signal can be active for as
little as 128 PCI clocks or as much as 896 PCI clocks. The actual slowdown (and
cooling) of the processor depends on the instruction stream, because the processor is
allowed to finish the current instruction. Furthermore, the ICH7 waits for the STOP-
GRANT cycle before starting the count of the time the STPCLK# signal is active.
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Intel ^® ICH7 Family Datasheet