307013-003 Datasheet, PDF (568/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.2.2.2
Note:
USB2.0_STS—USB 2.0 Status Register
Offset:
MEM_BASE + 24h–27h
Default Value: 00001000h
Attribute:
Size:
R/WC, RO
32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit
Description
31:16 Reserved. These bits are reserved and should be set to 0 when writing this register.
Asynchronous Schedule Status ⎯ RO. This bit reports the current real status of the
Asynchronous Schedule.
0 = Status of the Asynchronous Schedule is disabled. (Default)
1 = Status of the Asynchronous Schedule is enabled.
15
NOTE: The Host controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous Schedule
Enable bit (D29:F7:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD register. When
this bit and the Asynchronous Schedule Enable bit are the same value, the
Asynchronous Schedule is either enabled (1) or disabled (0).
Periodic Schedule Status ⎯ RO. This bit reports the current real status of the Periodic
Schedule.
0 = Status of the Periodic Schedule is disabled. (Default)
1 = Status of the Periodic Schedule is enabled.
14
NOTE: The Host controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit
(D29:F7:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit
and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
Reclamation ⎯ RO. 0=Default. This read-only status bit is used to detect an empty
13 asynchronous schedule. The operational model and valid transitions for this bit are
described in Section 4 of the EHCI Specification.
HCHalted ⎯ RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
12 _{1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the}
Run/Stop bit being set to 0, either by software or by the Host controller hardware
(e.g., internal error). (Default)
11:6 Reserved
Interrupt on Async Advance — R/WC. 0=Default. System software can force the host
controller to issue an interrupt the next time the host controller advances the
5 asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit
(D29:F7:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the
assertion of that interrupt source.
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Intel ^® ICH7 Family Datasheet