307013-003 Datasheet, PDF (695/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.48 VCH—Virtual Channel Capability Header Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 100h–103h
Default Value: 18010002h
Attribute:
Size:
RO
32 bits
Bit
Description
31:20 Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
19:16
Capability Version (CV) — RO. This field indicates that this is version 1 of the capability
structure by the PCI SIG.
15:0
Capability ID (CID) — RO. This field indicates that this is the Virtual Channel capability
item.
18.1.49 VCAP2—Virtual Channel Capability 2 Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 108h–10Bh
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
VC Arbitration Table Offset (ATO) — RO. This field indicates that no table is present for
VC arbitration since it is fixed.
23:0 Reserved.
18.1.50 PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 10Ch–10Dh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:4
3:1
0
Reserved.
VC Arbitration Select (AS) — R/W. This field indicates which VC should be
programmed in the VC arbitration table. The root port takes no action on the setting of
this field since there is no arbitration table.
Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table
programmed should be loaded into the VC arbitration table. This bit always returns 0
when read.
Intel ^® ICH7 Family Datasheet
695