307013-003 Datasheet, PDF (708/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.3
PCICMD—PCI Command Register
(Intel^® High Definition Audio Controller—D27:F0)
Offset Address: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
15:11
10
Description
Reserved
Interrupt Disable (ID) — R/W.
0= The INTx# signals may be asserted.
1= The Intel^® High Definition Audio controller’s INTx# signal will be de-asserted
NOTE: This bit does not affect the generation of MSIs.
9
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
8
SERR# Enable (SERR_EN) — R/W. SERR# is not generated by the Intel^® ICH7 Intel
High Definition Audio Controller.
7
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
6
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
5
VGA Palette Snoop (VPS). Not implemented. Hardwired to 0.
4
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to
0.
3
Special Cycle Enable (SCE). Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. Controls standard PCI Express* bus mastering
capabilities for Memory and I/O, reads and writes. Note that this bit also controls MSI
2
generation since MSIs are essentially memory writes.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — R/W. Enables memory space addresses to the
Intel High Definition Audio controller.
1
0 = Disable
1 = Enable
0
I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio
controller does not implement I/O space.
708
Intel ^® ICH7 Family Datasheet