307013-003 Datasheet, PDF (588/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.1.14 HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
14.2
Bit
Description
7:3 Reserved
I²C_EN — R/W.
2
0 = SMBus behavior.
1 = The Intel^® ICH7 is enabled to communicate with I²C devices. This will change the
formatting of some commands.
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer
to Section 5.21.4 (Interrupts / SMI#). This bit needs to be set for SMBALERT# to
be enabled.
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
0
1 = Enable. The SMB Host controller interface is enabled to execute commands. The
INTREN bit (offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host
controller to interrupt or SMI#. Note that the SMB Host controller will not respond
to any new requests until all interrupt requests have been cleared.
SMBus I/O Registers
Table 14-2. SMBus I/O Register Address Map
SMB_BASE
+ Offset
Mnemonic
Register Name
00h
HST_STS
Host Status
02h
03h
04h
05h
06h
07h
08h
09h
0Ah–0Bh
0Ch
0Dh
0Eh
HST_CNT
Host Control
HST_CMD
Host Command
XMIT_SLVA
Transmit Slave Address
HST_D0
Host Data 0
HST_D1
Host Data 1
HOST_BLOCK_DB Host Block Data Byte
PEC
Packet Error Check
RCV_SLVA
Receive Slave Address
SLV_DATA
Receive Slave Data
AUX_STS
Auxiliary Status
AUX_CTL
Auxiliary Control
SMLINK_PIN_CTL
SMLink Pin Control (TCO
Compatible Mode)
Default
Type
00h
00h
00h
00h
00h
00h
00h
00h
44h
0000h
00h
00h
See
register
description
R/WC, RO,
R/WC
(special)
R/W, WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/WC, RO
R/W
R/W, RO
588
Intel ^® ICH7 Family Datasheet