307013-003 Datasheet, PDF (542/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bit
Description
15:0
Error (ERR) — R/WC. The ERR field contains error information for use by host
software in determining the appropriate response to the error condition.
If one or more of bits 11:8 of this register are set, the controller will stop the current
transfer.
Bits Description
15:12Reserved
11 Internal Error (E): The SATA controller failed due to a master or target abort
when attempting to access system memory.
10 Protocol Error (P): A violation of the Serial ATA protocol was detected. Note:
The ICH7 does not set this bit for all protocol violations that may occur on the
SATA link.
9 Persistent Communication or Data Integrity Error (C): A communication
error that was not recovered occurred that is expected to be persistent.
Persistent communications errors may arise from faulty interconnect with the
device, from a device that has been removed or has failed, or a number of other
causes.
8 Transient Data Integrity Error (T): A data integrity error occurred that was
not recovered by the interface.
7:2 Reserved
1 Recovered Communications Error (M): Communications between the device
and host was temporarily lost but was re-established. This can arise from a
device temporarily being removed, from a temporary loss of Phy synchronization,
or from other causes and may be derived from the PhyNRdy signal between the
Phy and Link layers.
0 Recovered Data Integrity Error (I): A data integrity error occurred that was
recovered by the interface through a retry operation or other recovery action.
12.3.2.13 PxSACT—Port [3:0] Serial ATA Active (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 134h
Attribute:
R/W
Port 1: ABAR + 1B4h (ICH7R and ICH7DH Only)
Port 2: ABAR + 234h
Port 3: ABAR + 2B4h (ICH7R and ICH7DH Only)
00000000h
Size:
32 bits
Bit
31:0
Description
Device Status (DS) — R/W. System software sets this bit for SATA queuing operations
prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared via
the Set Device Bits FIS.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software, and as a result of a COMRESET or SRST.
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Intel ^® ICH7 Family Datasheet