307013-003 Datasheet, PDF (754/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.40 SDLVI—Stream Descriptor Last Valid Index Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 8Ch
Input Stream[1]: HDBAR + ACh
Input Stream[2]: HDBAR + CCh
Input Stream[3]: HDBAR + ECh
Output Stream[0]: HDBAR + 10Ch
Output Stream[1]: HDBAR + 12Ch
Output Stream[2]: HDBAR + 14Ch
Output Stream[3]: HDBAR + 16Ch
Attribute: R/W
Default Value: 0000h
Size:
16 bits
Bit
Description
15:8
7:0
Reserved.
Last Valid Index — R/W. The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it
will wrap back to the first descriptor in the list and continue processing.
This field must be at least 1 (i.e., there must be at least 2 valid entries in the buffer
descriptor list before DMA operations can begin).
This value should only be modified when the RUN bit is 0.
19.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 8Eh
Input Stream[1]: HDBAR + AEh
Input Stream[2]: HDBAR + CEh
Input Stream[3]: HDBAR + EEh
Output Stream[0]: HDBAR + 10Eh
Output Stream[1]: HDBAR + 12Eh
Output Stream[2]: HDBAR + 14Eh
Output Stream[3]: HDBAR + 16Eh
Attribute: R/W
Default Value: 0004h
Size:
16 bits
Bit
Description
15:3
2:0
Reserved.
FIFO Watermark (FIFOW) — R/W. This field indicates the minimum number of bytes
accumulated/free in the FIFO before the controller will start a fetch/eviction of data.
010 = 8B
011 = 16B
100 = 32B (Default)
Others = Unsupported
NOTES:
1.
When the bit field is programmed to an unsupported size, the hardware sets
itself to the default value.
2.
Software must read the bit field to test if the value is supported after setting the
bit field.
754
Intel ^® ICH7 Family Datasheet