307013-003 Datasheet, PDF (590/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
Bit
Description
FAILED — R/WC.
4
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in
response to the KILL bit being set to terminate the host transaction.
BUS_ERR — R/WC.
3 _{0 = Software clears this bit by writing a 1 to it.}
1 = The source of the interrupt of SMI# was a transaction collision.
DEV_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it. The ICH7 will then deassert the
interrupt or SMI#.
2 1 = The source of the interrupt or SMI# was due to one of the following:
• Invalid Command Field,
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.
INTR — R/WC (special). This bit can only be set by termination of a command. INTR is
not dependent on the INTREN bit (offset SMBASE + 02h, bit 0) of the Host controller
register (offset 02h). It is only dependent on the termination of the command. If the
INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be
1 ^{generated. Software can poll the INTR bit in this non-interrupt case.}
0 = Software clears this bit by writing a 1 to it. The ICH7 then deasserts the interrupt
or SMI#.
1 = The source of the interrupt or SMI# was the successful completion of its last
command.
HOST_BUSY — RO.
0 = Cleared by the ICH7 when the current transaction is completed.
1 = Indicates that the ICH7 is running a command from the host interface. No SMB
0
registers should be accessed while this bit is set, except the BLOCK DATA BYTE
Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only
when the SMB_CMD bits in the Host Control Register are programmed for Block
command or I²C Read command. This is necessary in order to check the
DONE_STS bit.
590
Intel ^® ICH7 Family Datasheet