307013-003 Datasheet, PDF (380/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
Note:
Bit
Description
FWH_60_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
2 _{1 = Enable the following ranges for the Firmware Hub}
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FWH_50_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 _{1 = Enable the following ranges for the Firmware Hub}
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FWH_40_EN — R/W. Enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
0 _{1 = Enable the following ranges for the Firmware Hub}
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
This register effects the BIOS decode regardless of whether the BIOS is resident on LPC
or SPI (Desktop and Mobile Only). The concept of Feature Space does not apply to SPI-
based flash. The ICH7simply decodes these ranges as memory accesses when enabled
for the SPI flash interface.
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Intel ^® ICH7 Family Datasheet