307013-003 Datasheet, PDF (591/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.2.2
Note:
HST_CNT—Host Control Register (SMBUS—D31:F3)
Register Offset: SMBASE + 02h
Default Value: 00h
Attribute:
Size:
R/W, WO
8-bits
A read to this register will clear the byte pointer of the 32-byte buffer.
Bit
Description
PEC_EN — R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase
appended.
7 _{1 = Causes the host controller to perform the SMBus transaction with the Packet Error}
Checking phase appended. For writes, the value of the PEC byte is transferred from
the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit
must be written prior to the write in which the START bit is set.
START — WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status
6
register (offset 00h) can be used to identify when the Intel^® ICH7 has finished the
command.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All
registers should be setup prior to writing a 1 to this bit position.
LAST_BYTE — WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be
received for the block. This causes the ICH7 to send a NACK (instead of an ACK)
5
after receiving the last byte.
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h,
bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is
set, the LAST_BYTE bit cannot be cleared. This prevents the ICH7 from running
some of the SMBus commands (Block Read/Write, I²C Read, Block I²C Write).
Intel ^® ICH7 Family Datasheet
591