307013-003 Datasheet, PDF (664/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
Note:
Note:
Bit
Description
Modem Out Interrupt (MOINT) — RO.
2 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the modem out channel interrupts status bits has been set.
Modem In Interrupt (MIINT) — RO.
1 _{0 = When the specific status bit is cleared, this bit will be cleared.}
1 = One of the modem in channel interrupts status bits has been set.
GPI Status Change Interrupt (GSCI) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set.
0
This indicates that one of the GPI’s changed state, and that the new values are
available in slot 12.
NOTE: This bit is not affected by AC ‘97 Audio Modem function D3_HOT to D0 Reset.
On reads from a codec, the controller will give the codec a maximum of four frames to
respond, after which if no response is received, it will return a dummy read completion
to the processor (with all F’s on the data) and also set the Read Completion Status bit
in the Global Status Register.
Reads across DWord boundaries are not supported.
17.2.10 CAS—Codec Access Semaphore Register
(Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
NABMBAR + 44h
00h
No
Attribute:
Size:
Power Well:
R/W (special)
8 bits
Core
Note:
Bit
Description
7:1 Reserved
Codec Access Semaphore (CAS) — R/W (special). This bit is read by software to
check whether a codec access is currently in progress.
0
0 = No access in progress.
1 = The act of reading this register sets this bit to 1. The driver that read this bit can
then perform an I/O access. Once the access is completed, hardware automatically
clears this bit.
Reads across DWord boundaries are not supported.
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Intel ^® ICH7 Family Datasheet