307013-003 Datasheet, PDF (492/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.4
Note:
Bit
Description
Bus Master Enable (BME) — R/W. This bit controls the ICH7’s ability to act as a PCI
2 master for IDE Bus Master transfers. This bit does not impact the generation of
completions for split transaction commands.
Intel^® ICH7R/ICH7DH/ICH7-M/ICH7-M DH Only:
Memory Space Enable (MSE) — R/W / RO. This bit controls access to the SATA
controller’s target memory space (for AHCI).
NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO).
1
Software is responsible for clearing this bit before entering combined mode.
ICH7 Only:
For the 82801GB ICH7, this bit is RO as 0, unless the SCRAE bit (offset 94h:bit 9) is
set.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
0
well as the Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
PCISTS — PCI Status Register (SATA–D31:F2)
Address Offset: 06h–07h
Default Value: 02B0h
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
15
14
13
12
11
10:9
8
7
6
5
Description
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
Reserved as 0 — RO.
Signaled Target Abort (STA) — RO. Reserved as 0.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED) — RO. For Intel^® ICH7, this bit can only be set
on read completions received from SiBUS where there is a parity error.
0 = Data parity error Not detected.
1 = SATA controller, as a master, either detects a parity error or sees the parity error
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 1.
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Intel ^® ICH7 Family Datasheet