307013-003 Datasheet, PDF (709/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.1.4
PCISTS—PCI Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Offset Address: 06h–07h
Default Value: 0010h
Attribute:
Size:
RO, R/WC
16 bits
19.1.5
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
SERR# Status (SERRS) — RO. Not implemented. Hardwired to 0.
Received Master Abort (RMA) — R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort received.
1 = The Intel^® High Definition Audio controller sets this bit when, as a bus master, it
receives a master abort. When set, the Intel High Definition Audio controller
clears the run bit for the channel that received the abort.
Received Target Abort (RTA) — RO. Not implemented. Hardwired to 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. Does not apply. Hardwired to 0.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Does not apply. Hardwired to 0.
Reserved.
66 MHz Capable (66MHZ_CAP) — RO. Does not apply. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 1. Indicates that the controller
contains a capabilities pointer list. The first item is pointed to by looking at
configuration offset 34h.
Interrupt Status (IS) — RO.
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Note that this bit is not set by an MSI.
Reserved.
RID—Revision Identification Register
(Intel^® High Definition Audio Controller—D27:F0)
Offset:
08h
Default Value: See bit description
Attribute:
Size:
RO
8 Bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
Intel ^® ICH7 Family Datasheet
709