307013-003 Datasheet, PDF (218/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5. If valid packet was received from the device that was more than one byte in length
(indicating it was a data packet), then the debug port controller:
— Transmits an ACK handshake packet
— Resets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit
6. If no valid packet is received, then the debug port controller:
— Sets the EXCEPTION_STS field to 001b
— Sets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit.
5.20.10.1.3 Debug Software
Enabling the Debug Port
There are two mutually exclusive conditions that debug software must address as part
of its startup processing:
• The EHCI has been initialized by system software
• The EHCI has not been initialized by system software
Debug software can determine the current ‘initialized’ state of the EHCI by examining
the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then
system software has initialized the EHCI. Otherwise the EHCI should not be considered
initialized. Debug software will initialize the debug port registers depending on the
state the EHCI. However, before this can be accomplished, debug software must
determine which root USB port is designated as the debug port.
Determining the Debug Port
Debug software can easily determine which USB root port has been designated as the
debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters
register. This 4-bit field represents the numeric value assigned to the debug port (i.e.,
0001=port 0).
Debug Software Startup with Non-Initialized EHCI
Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,
the Current Connect Status bit in the appropriate (See Determining the Debug Port)
PORTSC register is set. If the Current Connect Status bit is not set, then debug
software may choose to terminate or it may choose to wait until a device is connected.
If a device is connected to the port, then debug software must reset/enable the port.
Debug software does this by setting and then clearing the Port Reset bit the PORTSC
register. To ensure a successful reset, debug software should wait at least 50 ms before
clearing the Port Reset bit. Due to possible delays, this bit may not change to 0
immediately; reset is complete when this bit reads as 0. Software must not continue
until this bit reads 0.
If a high-speed device is attached, the EHCI will automatically set the Port Enabled/
Disabled bit in the PORTSC register and the debug software can proceed. Debug
software should set the ENABLED_CNT bit in the Debug Port Control/Status register,
and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the
system host controller driver does not see an enabled port when it is first loaded).
218
Intel ^® ICH7 Family Datasheet