307013-003 Datasheet, PDF (297/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
Bit
Description
6
(Desktop Reserved
Only)
No Reboot (NR) — R/W. This bit is set when the “No Reboot” strap (SPKR pin on
Intel^® ICH7) is sampled high on PWROK. This bit may be set or cleared by software if
the strap is sampled low but may not override the strap when it indicates “No
5
Reboot”.
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but
will not reboot on the second timeout.
Alternate Access Mode Enable (AME) — R/W.
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can
be read. Before entering a low power state, several registers from powered down
4
parts may need to be saved. In the majority of cases, this is not an issue, as
registers have read and write paths. However, several of the ISA compatible
registers are either read only or write only. To get data out of write-only
registers, and to restore data into read-only registers, the ICH7 implements an
alternate access mode. For a list of these registers see Section 5.14.10.
3
Reserved.
Reserved Page Route (RPR) — R/W. This bit determines where to send the
reserved page registers. These addresses are sent to PCI or LPC for the purpose of
generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h,
86h, 88h, 8Ch, 8Dh, and 8Eh.
0 = Writes will be forwarded to LPC, shadowed within the ICH7, and reads will be
returned from the internal shadow
2
1 = Writes will be forwarded to PCI, shadowed within the ICH7, and reads will be
returned from the internal shadow.
NOTE: If some writes are completed to LPC/PCI to these I/O ranges, and then this
bit is flipped such that writes will now go to the other interface, the reads will
not return what was last written. Shadowing is performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are
always decoded to LPC.
1
Reserved
BIOS Interface Lock-Down (BILD) — R/WLO.
0
0 = Disabled.
1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10)
from being changed. This bit can only be written from 0 to 1 once.
Intel ^® ICH7 Family Datasheet
297