307013-003 Datasheet, PDF (76/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-22. Power and Ground Signals (Sheet 3 of 3)
Name
Description
VccRTC
This pin provides the 3.3 V (can drop to 2.0 V min. in G3 state) supply for the
RTC well (1 pin). This power is not expected to be shut off unless the RTC
battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low. Clearing CMOS in an Intel^® ICH7-based platform can be
done by using a jumper on RTCRST# or GPI.
VccUSBPLL This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
(Desktop and for the USB PLL. This power may be shut off in S3, S4, S5 or G3 states. Must be
Mobile Only) powered even if USB not used.
VccDMIPLL
This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
for the DMI PLL. This power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL This pin provides the 1.5 V supply for core well logic (1 pin). This signal is used
(Desktop and for the SATA PLL. This power may be shut off in S3, S4, S5 or G3 states. Must
Mobile Only) be powered even if SATA not used.
V_CPU_IO
These pins are powered by the same supply as the processor I/O voltage (3
pins). This supply is used to drive the processor interface signals listed in
Table 2-13.
Vss
Grounds (194 pins).
2.24 Pin Straps
2.24.1 Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
Table 2-23. Functional Strap Definitions (Sheet 1 of 3)
Signal
Usage
When
Sampled
Comment
ACZ_SDOUT
ACZ_SYNC
EE_CS
(Desktop
and Mobile
Only)
XOR Chain
Entrance /
PCI
Express*
Port Config
bit 1
PCI Express
Port Config
bit 0
Reserved
Rising Edge of
PWROK
Rising Edge of
PWROK
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK. See Chapter 25
for XOR Chain functionality information.
When TP3 not pulled low at rising edge of PWROK,
sets bit 1 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See Section 7.1.34 for
details.
This signal has a weak internal pull-down.
This signal has a weak internal pull-down.
Sets bit 0 of RPC.PC (Chipset Configuration
Registers:Offset 224h). See Section 7.1.34 for
details.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
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Intel ^® ICH7 Family Datasheet