307013-003 Datasheet, PDF (636/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.2.3
x_LVI—Last Valid Index Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 05h (PILVI),
NABMBAR + 15h (POLVI),
NABMBAR + 25h (MCLVI)
MBBAR + 45h (MC2LVI)
MBBAR + 55h (PI2LVI)
MBBAR + 65h (SPLVI)
00h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 8-bit read to offset 05h.
16.2.4
Bit
Description
7:5 Hardwired to 0.
Last Valid Index [4:0] — R/W. This value represents the last valid descriptor in the
4:0 list. This value is updated by the software each time it prepares a new buffer and adds
it to the list.
NOTE: Reads across DWord boundaries are not supported.
x_SR—Status Register (Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
NABMBAR + 06h (PISR),
NABMBAR + 16h (POSR),
NABMBAR + 26h (MCSR)
MBBAR + 46h (MC2SR)
MBBAR + 56h (PI2SR)
MBBAR + 66h (SPSR)
0001h
No
Attribute:
Size:
Power Well:
R/WC, RO
16 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by
performing a single, 32-bit read from address offset 04h. Software can also read this
register individually by doing a single, 16-bit read to offset 06h. Reads across DWord
boundaries are not supported.
636
Intel ^® ICH7 Family Datasheet