307013-003 Datasheet, PDF (667/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.1
VID—Vendor Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 00h–01h
Default Value: 8086h
Attribute:
Size:
RO
16 bits
18.1.2
Bit
15:0
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel
DID—Device Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset:
Default Value:
02h–03h
Port 1= Bit Description
Port 2= Bit Description
Port 3= Bit Description
Port 4= Bit Description
Port 5= Bit Description
Port 6= Bit Description
Attribute:
Size:
RO
16 bits
18.1.3
Bit
15:0
Description
Device ID — RO. This is a 16-bit value assigned to the Intel^® ICH7 PCI Express
controller. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification Update
for the value of the Device ID Register.
PCICMD—PCI Command Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 04h–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11 Reserved
Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts on enabled
Hot-Plug and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
power management and MSI is not enabled.
10 _{1 = Internal INTx# messages will not be generated.}
NOTE: This bit does not affect interrupt forwarding from devices connected to the root
port. Assert_INTx and Deassert_INTx messages will still be forwarded to the
internal interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE) — Reserved per the PCI Express* Base Specification.
SERR# Enable (SEE) — R/W.
8 _{0 = Disable.}
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
7 Wait Cycle Control (WCC) — Reserved per the PCI Express Base Specification.
Parity Error Response (PER) — R/W.
6 ^{0 = Disable.}
1 = Indicates that the device is capable of reporting parity errors as a master on the
backbone.
Intel ^® ICH7 Family Datasheet
667